1. Field of the Invention
The present invention relates to a summation circuit and more particularly, an address transition detection summation circuit.
2. Background of the Related Art
FIG. 1 illustrates a related art address transition detection summation circuit. As shown in FIG. 1, the related art address transition detection summation circuit includes a first inverter IN1 and a second inverter IN2 connected in parallel to respectively invert a chip enable signal CSB. A PMOS transistor P1 has a source receiving a power supply voltage Vcc and a drain connected to a node ATDSO and performs a pull-up function. An address transition detection summation unit 10 formed in a wired-OR type is provided with a plurality of NMOS transistors N1 to Nn. The NMOS transistors N1 to Nn include gates that respectively receive an address transition detection (ATD) signal ATD1 to ATDn, sources respectively connected to a ground voltage Vss, drains connected in parallel to the node ATDS0 and perform a pull-down function. The address transition detection summation unit 10 sums an output from the PMOS transistor P1 and outputs from the plurality of NMOS transistors N1 to Nn.
The address transition detection summation circuit further includes a delay unit 20 having third through sixth inverters IN3-IN6 connected in series to delay a signal from the node ATDS0 and determine a pulse width of an address transition detection summation signal. A seventh inverter IN7 inverts an output from the delay unit 20. A NAND gate NA1 performs a NAND operation of a pair of outputs respectively received from the seventh inverter IN7 and the first inverter IN1 and transmits an output signal to a gate of the pull-up PMOS transistor P1. A signal output unit 30, includes eighth and ninth inverters IN8-IN9 connected in series to an output side of the node ATDS0 to output a final address transition detection summation signal ATDSUM. The number of inverters in the delay unit 20 and the signal output unit 30 is an even number.
The operation of the related art address transition detection summation circuit will now be described. As shown in FIG. 2A, when a normal ATD signal is inputted to the address transition detection summation unit 10, the node ATDS0, which is initially at a high level in the early stage, is pulled down and becomes a low level.
After a signal from the node ATDS0 is delayed by the delay unit 20, it is input to the seventh inverter IN7. When an output from the NAND NA1, which receives a signal inverted by the seventh inverter IN7 and an output signal from the first inverter IN1, becomes a low level, the pull-up PMOS transistor P1 is turned on and the node ATDS0 again becomes a high level. The address transition detection summation signal ATDSUM is then generated as an output from the signal output unit 30. As shown in FIG. 2B, when the PMOS transistor P1 is turned on, an input voltage level becomes a high level (Vcc).
As shown in FIG. 2C, when an ATD signal of a short pulse, which has an amplitude modulation at an intermediate level, is inputted to the address transition detection summation unit 10, a driving force of the pull-up PMOS transistor P1 is greater than that of the plurality of pull-down NMOS transistors N1 to Nn receiving the short pulse. Upon summing address transition detection signals for the short pulse ATD signal, the node ATDS0 maintains a high level by receiving an output from the pull-up PMOS transistor P1. Accordingly, as shown in FIG. 2C, a signal width of the final address transition detection summation signal ATDSUM does not enlarge lengthen).
When the ATD signal of the short pulse is inputted, for example, to a decoding unit of a SRAM circuit (not illustrated), a decoding signal responds to the short pulse, whereby a word line signal or a column select signal is converted and used to select a memory cell. In addition, in a control unit (not illustrated), an address transition detection summation signal controlling an internal circuit responds to the ATD signal of the short pulse, to drive an external circuit.
However, the related art addresses transition detection summation circuit has various disadvantages. When a pull-up PMOS transistor P1 is turned on and a ATD signal of a short pulse is inputted to the related art address transition detection summation circuit, a gate input voltage of the PMOS transistor P1 becomes the high level voltage, Vcc. Therefore, a driving force of the PMOS transistor P1 becomes greater than that of the plurality of NMOS transistors N1 to Nn that receive the short pulse. Thus, a pulse width of the final address transition detection summation signal ATDSUM does not enlarge as wide as the short pulse. Accordingly, the final address transition detection summation signal controlling the internal circuit is not able to respond to the ATD signal of the short pulse, whereby a decoding signal and a control signal mismatch can cause a failure to a chip operation.